The present invention relates to the field of integrated circuits and more particularly to low-threshold-voltage devices used for improving the characteristics of timing paths within an integrated circuit chip.
Known integrated circuit chips contain a large number of transistors and interconnections. Given the large number of these devices, combined with ever-increasing chip operating frequency, fullchip timing analysis and timing convergence is a challenge when designing the integrated circuit chip. This design issue becomes even more challenging because every incremental change to the integrated circuit design affects both maximum timing (often referred to as maxtiming) and minimum timing paths.
For example, FIG. 1A, labeled prior art, shows a simplified example of some of the issues relating to inserting buffers into an integrated circuit design to address minimum timing issues. More specifically, an integrated circuit design includes a plurality of sources (e.g., source 1), a plurality of destinations, (e.g., destination 1, destination 2 and destination 3). Between the sources and destinations are a plurality of nodes (designated by “x”) as well as a plurality of paths between the sources and the nodes, between the nodes and other nodes and between the nodes and the destinations. With an actual integrated circuit design there are many sources and destinations and massive numbers of nodes and paths.
Each of the nodes includes an associated time slot. A time slot is a continuously repeating interval of time in which two nodes are able to communicate. When the timing at a particular node is either too fast (i.e., a signal arrives at a node before the node's time slot) or too slow (i.e., a signal arrives at a node after the node's time slot), then the node is said to have either a maximum time failure or a minimum time failure, respectively.
In known systems, buffers (e.g., buffer 1) are placed close to each of the destinations within the integrated circuit to address the minimum time failures for that particular destination. In some cases the addition of buffers might cause maxtime failures. Replacing standard threshold voltage (Vt) devices with low Vt devices is another known method of improving the characteristics of timing paths. For example, FIG. 1B, labeled prior art, shows a simplified example of some of the issues relating to inserting low Vt devices into an integrated circuit design to address minimum timing issues. However, usage of low Vt devices needs to be minimized to suppress leakage current, and an effective low Vt device replacement algorithm is required.
In integrated circuit design, timing convergence is tedious and prolonged due to the incremental nature of the timing fixes. Because buffers and low Vt devices can address a wide range of timing and electrical issues, many different types of buffers and/or low Vt devices are often used within a single integrated circuit design to address timing issues. A system that automates the process of addressing timing issues of buffers and/or low Vt devices within an integrated circuit design can reduce the design cycle for timing convergence. The algorithm implemented within the system provides a fast and efficient way to resolve timing issues.